xpla3 users guide, Gumowa logika, Xilinx, Narzędzia
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//-->RUser Manual UG004 (v1.0)March 10, 2000CoolRunner XPLA3 Development KitUser ManualIntroductionThe CoolRunner™ XPLA3™ Development Kit allows the designer to experiment with theXilinx CoolRunner XPLA3 architecture using In-System Programming (ISP) to configure thedevice. Using the Xilinx Parallel Download Cable III and the PC-ISP3 Programmer softwareavailable from Xilinx WebPACK attheCoolRunner XPLA3 device can be programmed on the board directly from any PC. AnyJEDEC file that targets the XCR3256XL can be downloaded to the board in this manner. TheXilinx Watch Tutorial can also be implemented on this XPLA3 Demo Board as described in theTutorial section of this document.This development kit consists of a Xilinx XPLA3 CoolRunner 256 macrocell device in a TQ144package which can be programmed using the included Xilinx Parallel Download Cable III.Several power sources can be used with this board which include a +3.3V regulated input andtwo +10.0V maximum unregulated inputs. For low power demonstrations, this board can also bepowered using grapefruits as shown inFigure 1.This is discussed later in this document in theGrapefruit Demonstration section. Two clock sources are available to the CoolRunner which canbe either the 32.768 kHz low power on board clock or an external clock source (with an internalimpedance of 50 ohms). A prototyping area is also available so the designer can experiment withthe CoolRunner XPLA3 architecture while interfacing to external components.Figure 1:CoolRunner XPLA3 Development Kit with Grapefruit Power Supply© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed atAll other trademarks and registered trademarks are the property of their respective owners.User Manual UG004 (v1.0) March 10, 2000www.xilinx.com1-800-255-77781CoolRunner XPLA3 Development Kit User ManualRGetting StartedImportant:Prior to powering the board the first time, please read the section entitled PowerConnections.A new CoolRunner XPLA3 Development Kit ships pre-programmed with a demonstration thatuses the LCD. The demonstration simply scrolls the word "CoolrunnEr" from right to left in theLCD. In order to view the CoolRunner demonstration, apply power to the board. Thedemonstration will immediately begin to run.To begin using the CoolRunner XPLA3 Development Kit follow the steps below.1. Connect the power source to the board as specified in the section entitled PowerConnections. The "CoolrunnEr" pattern should begin scrolling from right to left in theLCD.2. Connect the Xilinx Parallel Download Cable III to the JTAG port JP6 located on the righthand side of the board. The "flying wires" from this cable should be connected to the boardin a manner that the labels on the cables match the silk screen on the XPLA3 Demo Boardfor TCO, TCK, TMS, TDI, VDD and GND.3. Using the Xilinx PC-ISP3 Programmer software, available for download from WebPACKatthe board can be programmed with anycustom JEDEC file.FeaturesPower ConnectionsThe CoolRunner XPLA3 Development Kit is designed to provide the user with maximumflexibility when connecting the power supply. A +3.3V voltage regulator is mounted to theboard to allow for additional voltage flexibility. Along the right hand side of the board there arefour connections. Three of these are power connections for applying power and are labeled"V", "+3.3V", and "J2". An additional connection labeled "GND" is a large pad and is used toconnect ground to the board using an alligator clip type of connector. This type of pad will alsoallow the user to solder a wire to the board for a more permanent connection. The two powerconnections labeled "V" and "+3.3V" are also large pads and may be connected to the powersource in the same manner. Finally, the power connection labeled "J2" is a jack to accept theexternal AC power adapter shipped with the CoolRunner XPLA3 Development Kit.Located directly to the left of these power connections is JP7 which is used to manage thesepower connections.Figure 2displays the arrangement of the jumpers andTable 1describes thepositioning of these jumpers to properly operate the board.Jumper 7-8 on JP7 is used to conveniently connect or disconnect all power sources to the board.When the jumper is removed, power is disconnected from most components on the board.Power will still be present on JP7, the Voltage Regulator (U3), C1, and C2 which can be seenin the schematic as shown inFigure 6at the end of this document. In addition, this jumper canbe used for the grapefruit demo as discussed in the Grapefruit Demonstration section later inthis document.Before using the AC power adapter, configure JP7 as shown in the diagram labeled "ACAdapter" ofFigure 2.If using a battery pack or grapefruit as a power source, configure JP7 asshown in the diagram labeled "+3.3V Pad Input" ofFigure 2prior to connecting the powersource. If using any other external power source that needs to be regulated, configure JP7 asshown in the diagram labeled "+V Pad Input" ofFigure 2which will use the on board voltageregulator.2www.xilinx.com1-800-255-7778User Manual UG004 (v1.0) March 10, 2000CoolRunner XPLA3 Development Kit User ManualR121212343434565656787878AC Adapter+V PadInput+3.3V PadInputUG004_02_030100Figure 2:JP7 ArrangementTable 1:JP7 ConfigurationPins (Closed)FunctionDescription2-4Connects "+3.3V" Used when an externally regulated power source set topad to "VCC". +3.3V is connected to the "+3.3V" pad. This supplyvoltage must not to exceed the data sheet value for theXCR3256XL.Connects theoutput of the onboard regulator to"VCC".When using an unregulated power source connected tothe "V" pad or the "J2" connector, use this configurationto apply the output of the on board voltage regulator to"VCC".6-41-3Connects "V" pad When using an externally unregulated power sourceto the input of the connected to the "V" pad, use this configuration to applyon board regulator. the voltage to the input of the on board +3.3V voltageregulator. This externally applied voltage must be setbetween the limits of +4.8V min. to +10.0V max.Connects "J2"connector to theinput of the onboard regulator.When using the external AC power adapter connected tothe "J2" connector, use this configuration to apply thevoltage to the input of the on board +3.3V voltageregulator. This externally applied voltage must be setbetween the limits of +4.8V min. to +10.0V max. Thesupplied AC power adapter typically delivers anunregulated +6.0V.5-37-8Connects "VCC" Used to connect/disconnect all power sources to theto the board’sboard after JP7 and the on board regulator. Duringpower plane.normal operation, this jumper must be closed. Whenusing grapefruit as a power source, this jumper must beopen for approximately 15 seconds with the grapefruitconnected. Then close the jumper to initiate power up.User Manual UG004 (v1.0) March 10, 2000www.xilinx.com1-800-255-77783CoolRunner XPLA3 Development Kit User ManualRClockingDevices on the XPLA3 Demo Board can be clocked from either the on board 32.768 kHz lowpower clock or an external clock source. Selection between the two clock sources isaccomplished by the position of JP5.Figure 3shows the positioning of JP5 to select eitherclock source.EXT3EXT3CLK2CLK2INT1INT1InternalClockExternalClockUG004_03_030100Figure 3:JP5 ArrangementTo use the external clock, a BNC PCB mount connector must be separately purchased andsoldered to the space provided at J1 on the XPLA3 Demo Board. Use AMP part number414460-1 or equivalent. Jumper J5 connects this clock to a 50 ohm trace. This clock network isconnected to CLK0 on the XPLA3 CoolRunner CPLD.Three additional clocks, CLK1, CLK2, and CLK3, are tied to the weak pull down resistors R5,R6, and R7 as shown inFigure 6.These are 51 ohm resistors intended to match a 50 ohm outputimpedance of the external clock source. These clocks may be accessed via JP1 pin 20, 19, 18,and 17 (CLK0, CLK1, CLK2, and CLK3 respectively) also shown inFigure 6.JTAG PortThe JTAG port JP6 connects the ISP pins of the CoolRunner to the computer via the XilinxParallel Download Cable III. Using the Xilinx PC-ISP3 Programmer software, the XPLA3CoolRunner can be accessed via this port for all ISP and JTAG operations. When using thecable, ensure that the labels on the "flying wires" match the silk screen on the XPLA3 DemoBoard to ensure proper operation.All ISP pins are directly connected to the JTAG port JP6 but are also available on selectedheaders as shown inTable 2.Table 2:JTAG Signal AccessJTAG PinHeaderHeader PinTMSTCKTDITDOJP2JP4JP2JP42017432In the event that the ISP pins were not reserved in the design, the JTAG port will no longer beaccessible and will therefore prevent the user from subsequent device programming. To gainaccess to the ISP pins once again, it will be necessary to temporarily pull the PORT_EN signal4www.xilinx.com1-800-255-7778User Manual UG004 (v1.0) March 10, 2000CoolRunner XPLA3 Development Kit User ManualRhigh before programming. This will allow the user to program the device with the JTAG port.This signal is accessible via JP2 PIN 13. Once the CoolRunner has been programmed in thismanner, the PORT_EN pin must be returned to the low state for normal operation.LCDThe on-board LCD has 16 segments arranged as shown inFigure 4.In the defaultconfiguration, the segments of the LCD are connected to the I/Os via jumpers LCD1 and LCD2as described inTable 1.By removing the jumpers, the I/Os will be disconnected from the LCDsegments.The LCD ground pin is connected to an I/O pin. Since the characteristic of LCDs is such that acharge builds up in the segment over time while held at DC levels, this board has been designedwith the ability to drive the LCD reference pin with an oscillating signal at approximately a50% duty cycle. A segment is darkened when driven by an inverted signal with respect to theLCD reference pin; a segment is transparent when driven by a signal in phase with the LCDreference pin signal. This technique is implemented in the "CoolrunnEr" demonstration pattern.FNGHEOPMBCADIJKLUG004_04_030100Figure 4:Segment Assignments for the LCDTable 1: LCD Jumper ArrangementLCD SegmentI/O NumberPin NumberJumperPins (Closed)ABCDEFGHIJKLIO58IO59IO60IO61IO62IO63IO64IO65IO67IO68IO69IO70747577787980818284868788LCD2LCD2LCD2LCD2LCD2LCD2LCD2LCD2LCD1LCD1LCD1LCD11-23-45-67-89-1011-1213-1415-161-23-45-67-8User Manual UG004 (v1.0) March 10, 2000www.xilinx.com1-800-255-77785
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