xc9536xl, pamieci , MEMORY PDFS w
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//-->RXC9536XL High PerformanceCPLD5DS058 (v1.4) August 21, 2003Preliminary Product SpecificationFeatures••••5 ns pin-to-pin logic delaysSystem frequency up to 178 MHz36 macrocells with 800 usable gatesAvailable in small footprint packages- 44-pin PLCC (34 user I/O pins)- 44-pin VQFP (34 user I/O pins)- 48-pin CSP (36 user I/O pins)- 64-pin VQFP (36 user I/O pins)Optimized for high-performance 3.3V systems- Low power operation- 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5Vsignals- 3.3V or 2.5V output capability- Advanced 0.35 micron feature size CMOSFast FLASH™ technologyAdvanced system features- In-system programmable- Superior pin-locking and routability withFast CONNECT™ II switch matrix- Extra wide 54-input Function Blocks- Up to 90 product-terms per macrocell withindividual product-term allocation- Local clock inversion with three global and oneproduct-term clocks- Individual output enable per output pin- Input hysteresis on all user and boundary-scan pininputs- Bus-hold circuitry on all user pin inputs- Full IEEE Standard 1149.1 boundary-scan (JTAG)Fast concurrent programmingSlew rate control on individual outputsEnhanced data security featuresExcellent quality and reliability- Endurance exceeding 10,000 program/erasecycles- 20 year data retention- ESD protection exceeding 2,000VPin-compatible with 5V-core XC9536 device in the44-pin PLCC package and the 48-pin CSP packagePower EstimationPower dissipation in CPLDs can vary substantially depend-ing on the system frequency, design application and outputloading. To help reduce power dissipation, each macrocellin a XC9500XL device may be configured for low-powermode (from the default high-performance mode). In addi-tion, unused product-terms and macrocells are automati-cally deactivated by the software to further conserve power.For a general estimate of ICC, the following equation may beused:ICC(mA) = MCHS(0.175*PTHS+ 0.345) + MCLP(0.052*PTLP+ 0.272) + 0.04 * MCTOG(MCHS+MCLP)* fwhere:MCHS= # macrocells in high-speed configurationPTHS= average number of high-speed product termsper macrocellMCLP= # macrocells in low power configurationPTLP= average number of low power product terms permacrocellf = maximum clock frequencyMCTOG = average % of flip-flops toggling per clock(~12%)This calculation was derived from laboratory measurementsof an XC9500XL part filled with 16-bit counters and allowinga single output (the LSB) to be enabled. The actual ICCvalue varies with the design application and should be veri-fied during normal system operation.Figure 1shows theabove estimation in a graphical form. For a more detaileddiscussion of power consumption in this device, see Xilinxapplication noteXAPP114, “Understanding XC9500XLCPLD Power.”7060Typical ICC(mA)••••••5040302010•HigehPrfornmace178 MHzDescriptionThe XC9536XL is a 3.3V CPLD targeted for high-perfor-mance, low-voltage applications in leading-edge communi-cations and computing systems. It is comprised of two54V18 Function Blocks, providing 800 usable gates withpropagation delays of 5 ns. SeeFigure 2for architectureoverview.LoowPwer125 MHz50100150200250Clock Frequency (MHz)DS058_01_121501Figure 1:Typical ICCvs. Frequency for XC9536XL© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed atAll other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.DS058 (v1.4) August 21, 2003Preliminary Product Specificationwww.xilinx.com1-800-255-77781XC9536XL High Performance CPLDR3JTAG Port1JTAGControllerIn-System Programming Controller54I/OI/OI/OFast CONNECT II Switch MatrixI/O541818FunctionBlock 1Macrocells1 to 18FunctionBlock 2Macrocells1 to 18I/OBlocksI/OI/OI/OI/O3I/O/GCK1I/O/GSRI/O/GTS2DS058_02_081500Figure 2:XC9536XL ArchitectureFunction Block outputs (indicated by the bold line) drive the I/O Blocks directly.2www.xilinx.com1-800-255-7778DS058 (v1.4) August 21, 2003Preliminary Product SpecificationRXC9536XL High Performance CPLDAbsolute Maximum RatingsSymbolVCCVINVTSTSTGTSOLTJDescriptionSupply voltage relative to GNDInput voltage relative to GND(1)Voltage applied to 3-state output(1)Storage temperature (ambient)Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)Junction temperatureValue–0.5 to 4.0–0.5 to 5.5–0.5 to 5.5–65 to +150+220+150UnitsVVVoCoCoCNotes:1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, thedevice pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with theforcing current being limited to 200 mA.2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditionsis not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.Recommended Operation ConditionsSymbolVCCINTVCCIOVILVIHVOParameterSupply voltage for internal logicand input buffersCommercial TA= 0oC to 70oCIndustrial TA= –40oC to +85oCMin3.03.03.02.32.0Max3.63.63.62.70.805.5VCCIOUnitsVVVVVVVSupply voltage for output drivers for 3.3V operationSupply voltage for output drivers for 2.5V operationLow-level input voltageHigh-level input voltageOutput voltageQuality and Reliability CharacteristicsSymbolTDRNPEVESDData RetentionProgram/Erase Cycles (Endurance)Electrostatic Discharge (ESD)ParameterMin2010,0002,000Max---UnitsYearsCyclesVoltsDC Characteristic Over Recommended Operating ConditionsSymbolVOHVOLIILIIHIIHParameterOutput high voltage for 3.3V outputsOutput high voltage for 2.5V outputsOutput low voltage for 3.3V outputsOutput low voltage for 2.5V outputsInput leakage currentI/O high-Z leakage currentI/O high-Z leakage currentTest ConditionsIOH= –4.0 mAIOH= –500µAIOL= 8.0 mAIOL= 500µAVCC= Max; VIN= GND or VCCVCC= Max; VIN= GND or VCCVCC= Max; VCCIO= Max;VIN= GND or 3.6VVCCMin < VIN< 5.5VCINICCI/O capacitanceOperating supply current(low power mode, active)VIN= GND; f = 1.0 MHzVIN= GND, No load; f = 1.0 MHzMin2.490% VCCIO-------10 (Typical)Max--0.40.4±10±10±10±5010UnitsVVVVµAµAµAµApFmADS058 (v1.4) August 21, 2003Preliminary Product Specificationwww.xilinx.com1-800-255-77783XC9536XL High Performance CPLDRAC CharacteristicsXC9536XL-5SymbolTPDTSUTHTCOTPSUTPHTPCOTOETODTPOETPODTAOTPAOTWLHTPLHI/O to output validI/O setup time before GCKI/O hold time after GCKGCK to output validI/O setup time before p-term clock inputI/O hold time after p-term clock inputP-term clock output validGTS to output validGTS to output disableProduct term OE to output enabledProduct term OE to output disabledGSR to output validP-term S/R to output validGCK pulse width (High or Low)P-term clock pulse width (High or Low)ParameterMin-3.7--1.72.0-------2.85.0Max5.0--3.5178.6--5.54.04.07.07.010.010.5--XC9536XL-7Min-4.8--1.63.2-------4.06.5Max7.5--4.5125--7.75.05.09.59.512.012.6--XC9536XL-10Min-6.5--2.14.4-------4.57.0Max10.0--5.8100--10.27.07.011.011.014.515.3--UnitsnsnsnsnsMHznsnsnsnsnsnsnsnsnsnsnsfSYSTEMMultiple FB internal operating frequencyVTESTR1Device OutputR2CLOutput TypeVCCIO3.3V2.5VVTEST3.3V2.5VR1320Ω250ΩR2360Ω660ΩCL35 pF35 pFDS058_03_081500Figure 3:AC Load Circuit4www.xilinx.com1-800-255-7778DS058 (v1.4) August 21, 2003Preliminary Product SpecificationRXC9536XL High Performance CPLDInternal Timing ParametersXC9536XL-5SymbolBuffer DelaysTINTGCKTGSRTGTSTOUTTENTPTCKTPTSRTPTTSTPDITSUITHITECSUTCOITAOITRAITLOGIInput buffer delayGCK buffer delayGSR buffer delayGTS buffer delayOutput buffer delayOutput buffer enable/disable delayProduct term clock delayProduct term set/reset delayProduct term 3-state delayCombinatorial logic propagation delayRegister setup timeRegister hold timeRegister clock enable setup timeRegister clock to output valid timeRegister async. S/R to output delayRegister async. S/R recover before clockInternal logic delay----------2.31.42.31.4--5.0-----1.05.01.90.73.01.51.12.04.02.01.61.05.50.5----0.46.0----------2.62.22.62.2--7.5-----1.46.43.50.84.02.31.53.15.02.52.41.47.21.3----0.56.4----------3.03.53.03.5--10.0-----1.87.34.21.04.53.51.84.57.03.02.71.87.51.7----1.07.0nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsParameterMinMaxXC9536XL-7MinMaxXC9536XL-10MinMaxUnitsProduct Term Control DelaysInternal Register and Combinatorial DelaysTECHORegister clock enable hold timeTLOGILPInternal low power logic delayFeedback DelaysTFTPTAFast CONNECT II feedback delayIncremental product term allocator delayTime AddersTSLEWSlew-rate limited delayDS058 (v1.4) August 21, 2003Preliminary Product Specificationwww.xilinx.com1-800-255-77785
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