z80, Ham- CB Radio, Karty katalogowe
[ Pobierz całość w formacie PDF ]
G<
(
1746*
)
'0'4#6+10
<
2
41%'5514
%
14'
2
41%'5514
&
'5%4+26+10
25</2
<K.1)9
14.&9+&’
*
’#&37#46’45
'*
#/+.610
#
8’07’
%
#/2$’..
%#
6
’.’2*10’
(
#:
+
06’40’6
*662
999
<
+
.1)
%1/
©1999 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applica-
tions, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC.
DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF
THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG
ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT
RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of life support systems is not authorized. No
licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
KK
G<
25</2
)
’0’4#.
&
’5%4+26+10
)'0'4#.&'5%4+26+10
The eZ80
â„¢
is ZiLOG’s next-generation Z80
â„¢
processor. The eZ80 provides 16
times the performance of a traditional Z80. The multiple operating modes of the
processor allows Z80 and Z180 code to be run without change in the same appli-
cation with new code, that takes advantage of the eZ80’s 16-MB linear addressing
space and enhanced instruction set. These features provide customers perfor-
mance comparable to 16-bit processors with the form factor and power savings of
an 8-bit processor. At the same time, the eZ80 remains 100% Z80 code-compat-
ible, reducing customer development time.
The eZ80 also features a Multiply and Accumulate engine, which enables
customers to attack signal-processing applications that require polynomial calcu-
lations, such as basic filters.
The eZ80 is internet-ready. ZiLOG can provide a complete TCP/IP stack,
allowing for rapid internet connectivity.
The eZ80 also features ZiLOG’s Debug Interface (ZDI). This two-pin interface
allows advanced debugging features without the cost and difficulty and uncer-
tainty of an in-circuit emulator.
The eZ80 is a licensable soft core, allowing rapid integration into designs.
&'6#+.'&&'5%4+26+10
Z80 High-Performance Microprocessor Core.
The eZ80
is one of the fastest 8-
bit CPUs available today, executing code 4 times faster than a standard Z80 oper-
ating at the same clock speed. The increased processing efficiency can be used to
improve available bandwidth or to decrease power consumption.
Both the increased clock speed and processor efficiency features provides eZ80
customers 16 times the processing performance. This processing power rivals
performance customers would normally expect from 16-bit microprocessors.
16 MB Linear Address.
The eZ80 is also the first 8-bit microprocessor to support
16 MB linear addressing—a feature that addresses large memories that support
complex software applications.
Each software module, or each task under a real-time executive or operating
system, can operate in Z80-compatible (64 KB) mode, Z80180-compatible mode
(1 MB MMU) mode, or full 24-bit (16 MB) address mode.
Internet-Ready.
A complete TCP/IP stack is also offered so customers can design
products that connect to the Internet.
Multiply and Accumulate.
A Multiply and Accumulate engine operates in
parallel with the eZ80 processor to calculate a sum of products that is the core of
digital signal processing. The MAC provides 16x16 multiply and 40-bit accumu-
lation.
ZDI.
The ZiLOG Debug Interface is a 2-pin communication port. When used with
the ZiLOG Develop Suite (ZDS) software, ZDI provides on-chip emulation.
25</2
G<
#
4%*+6’%674#.
1
8’48+’9
$
.1%-
&
+#)4#/
#4%*+6'%674#.18'48+'9
The eZ80 is ZiLOG’s fourth-generation Z80 processor core. It is the basis of a
new family of integrated microprocessors, and includes the following features:
•
Upward-code-compatible from Z80 & Z180
•
Several address-generation modes including 24-bit linear addressing
•
24-bit registers and ALU
•
One-clock-minimum bus cycles
•
Optional autonomous Multiply-Accumulate engine for DSP applications
$
.1%-
&
+#)4#/
is a block diagram of the eZ80.
#FFTGUU
5GNGEVKQP
4GIKUVGTU
#
#.7
//7
/$#5'
2%
&CVC
1WV
52
&
&CVC
+P
1P%JKR
4#/
/#%'PIKPG
%64.176
%QPVTQN
5VQTG
'ZGEWVKQP
%QPVTQN
%64.+0
<%.
<&#
<&+
(
+)74’
<$
.1%-
&
+#)4#/
2+0&'5%4+26+105
illustrates the logic diagram of the eZ80.
describes the processor
and device pins.
G<
25</2
’
 $
.1%-
&
+#)4#/
2
+0
&
’5%4+26+105
D7
D6
D5
D4
D3
D2
D1
D0
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MREQ
IO
RQ
RD
WR
MRD
MWR
IORD
IOWR
INTAK
BUSACK
IN
STRD
RETI
CLK
RESET
WAIT
NMI
INT0
BUSREQ
HALT
(
+)74’
’
<.
1)+%
&
+#)4#/
25</2
G<
Â
[ Pobierz całość w formacie PDF ]