wzmacniacz 500w ta0104a, Elektronika abc, ELEKTRONIKA
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Tripath Technology, Inc. - Technical Information
TA0104A
STEREO 500W (4
Ω
) CLASS-T DIGITAL AUDIO AMPLIFIER
DRIVER USING DIGITAL POWER PROCESSING (DPP
TM
)
TECHNOLOGY
Technical Information
Revision 3.1 – June 2000
GENERAL DESCRIPTION
The TA0104A is a 500W continuous average (4
Ω
), two channel Amplifier Driver
Module which uses Tripath’s proprietary Digital Power Processing (DPP
TM
)
technology. Class-T amplifiers offer both the audio fidelity of Class-AB and the
power efficiency of Class-D amplifiers.
APPLICATIONS
“Audiophile” Sound Quality
0.02% THD+N @ 300W, 8
Ω
0.02% IHF-IM @ 100W, 8
Ω
350W @ 8
Ω
, 0.1% THD+N,
Vs =
+
90V
500W @ 4
Ω
, 0.1% THD+N,
Vs =
+
90V
High Power
450W @ 8
Ω
, 1% THD+N,
Vs =
+
90V
750W @ 4
Ω
, 1% THD+N,
Vs =
+
90V
High Efficiency
90% @ 400W @ 8
Ω
,
Vs =
+
75V
85% @ 600W @ 4
Ω
, Vs =
+
75V
Dynamic Range = 106 dB
Requires only N-Channel MOSFET output transistors
High power supply rejection ratio
Mute input
Outputs short-circuit protected
Over- and under-voltage protection
Bridgeable, single-ended outputs
38-pin quad package
Supports 100kHz BW of Super Audio CD and DVD-
Audio (Refer to Application Note for specifics)
Audio/Video
Amplifiers/Receivers
Pro-audio Amplifiers
Automobile Power Amplifiers
Subwoofer Amplifiers
BENEFITS
Reduced system cost with smaller/less
expensive power supply and heat sink
Signal fidelity equal to high quality Class-AB
amplifiers
High dynamic range compatible with digital
media such as CD and DVD
Features
Class-T architecture
Proprietary Digital Power Processing
technology
Supports wide range of output power levels
TYPICAL PERFORMANCE AT
+
90V
THD+N vs Output Power
10
20Hz - 22kHz BW
f = 1kHz
BBM = 25nS
V
S
= +/-90V
Av = 200
ST STW38NB20 MOSFET
2
1
0.5
0.2
0.1
0.05
R
L
= 4
Ω
0.02
0.01
0.005
0.002
R
L
= 8
Ω
0.001
1
2
5
10
20
50
100
200
500
1K
Output Power (W)
1
TA104A – Rev. 3.1/06.00
5
Tripath Technology, Inc. - Technical Information
Absolute Maximum Ratings
SYMBOL
PARAMETER
Value
UNITS
Vs
Supply Voltage (Vspos & Vsneg)
+/-100
V
V5
Positive 5 V Bias Supply
6
V
VN12
Reference Voltage: Nominal +12V referenced to Vsneg
18
V
T
STORE
Storage Temperature Range
-40 to 150
ºC
T
A
Operating Free-air Temperature Range
-20 to +80
ºC
Notes: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Damage will occur to the device if VN12 is not supplied or falls below the recommended
operating voltage when V
S
is within its recommended operating range.
Operatin
g Conditions
SYMBOL
PARAMETER
MIN. TYP. MAX. UNITS
Vs
Supply Voltage (Vspos & Vsneg) +/- 55 +/- 75 +/- 92 V
V5 Positive 5 V Bias Supply 4.5 5 5.5 V
VN12 Reference Voltage: Nominal +12V referenced to Vsneg 10.8 12 13.2 V
Note: Recommended Operating Conditions indicate conditions for which the device is functional. See Electrical
Characteristics for guaranteed specific performance limits.
Electrical Characteristics
T
A
= 25
°
C. See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.
SYMBOL
PARAMETER
MIN. TYP. MAX. UNITS
I
q
Quiescent Current
+67V
50
50
45
170
mA
mA
mA
mA
(no load, BBM0=BBM1=0)
-67V
+5V
VN12
I
S
Source Current @ P
OUT
= 250W, R
L
= 4
Ω
V
SPOS
= +67V
@ 10% THD+N
4.2
4.2
A
A
V
SNEG
= -67V
I5
Source Current for 5V Bias Supply @ P
OUT
= 250W, R
L
= 4
Ω
50
mA
IVN12
Source Current for VN12 Supply @ P
OUT
= 250W, R
L
= 4
Ω
80
mA
Vu
Under Voltage (Vspos & Vsneg)
+/-55
V
Vo
Over Voltage (Vspos & Vsneg)
+/-92
V
V
IH
High-level Input Voltage (MUTE)
3.5
V
V
IL
Low-level Input Voltage (MUTE)
1
V
I
DD
MUTE
Mute Supply Current
+67V
0
0
15
0
mA
mA
mA
mA
(no load, BBM0=BBM1=0)
-67V
+5V
VN12
V
OH
High-level Output Voltage (HMUTE & OVERLOADB)
3.5
V
V
OL
Low-level Output Voltage (HMUTE & OVERLOADB)
1
V
V
TOC
Over Current Sense Voltage Threshold
0.67
0.75
0.82
V
A
V
Gain Ratio V
OUT
/V
IN
, R
IN
= 0
Ω
160
V/V
Voffset
Offset Voltage, no load, MUTE = Logic low
600
mV
Minimum and maximum limits are guaranteed but may not be 100% tested.
2
TA104A – Rev. 3.1/06.00
Tripath Technology, Inc. - Technical Information
Performance Characteristics – Single Ended, Vs =
+
90V
Unless otherwise specified, f = 1kHz, Measurement Bandwidth = 22kHz. T
A
= 25
°
C.
See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNITS
P
OUT
Output Pow er
(Continuous Average/Channel)
THD+N = 0.1%, R
L
= 8
Ω
R
L
= 4
Ω
THD+N = 1%, R
L
= 8
Ω
350
500
450
750
W
W
W
W
R
L
= 4
Ω
THD + N Total Harmonic Distortion Plus
Nois e
P
OUT
= 300W/Channel, R
L
= 8
Ω
0.02
%
IHF-IM
IHF Intermodulation Distortion
19kHz, 20kHz, 1:1 (IHF), R
L
= 8
Ω
P
OUT
= 100W/Channel
0.02
%
SNR
Signal-to-Noise Ratio
A Weighted, P
OUT
= 350W/Ch, R
L
= 8
Ω
100.5
dB
CS
Channel Separation
0dBr = 100W, R
L
= 8
Ω
85
dB
PSRR
Pow er Supply Rejection Ratio Input Ref erenced, 30kHz Bandw idth
65
dB
e
NOUT
Output Noise Voltage
A Weighted, no signal, input shorted, DC
of f set nulled to zero
500
µ
V
Performance Characteristics – Single Ended, Vs =
+
75V
Unless otherwise specified, f = 1kHz, Measurement Bandwidth = 22kHz. T
A
= 25
°
C.
See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNITS
P
OUT
Output Pow er
(Continuous Average/Channel)
THD+N = 0.1%, R
L
= 8
Ω
R
L
= 4
Ω
THD+N = 1%, R
L
= 8
Ω
200
425
300
500
W
W
W
W
R
L
= 4
Ω
THD + N Total Harmonic Distortion Plus
Nois e
P
OUT
= 300W/Channel, R
L
= 4
Ω
0.02
%
IHF-IM
IHF Intermodulation Distortion
19kHz, 20kHz, 1:1 (IHF), R
L
= 8
Ω
P
OUT
= 100W/Channel
0.02
%
SNR
Signal-to-Noise Ratio
A Weighted, P
OUT
= 200W/Ch, R
L
= 8
Ω
98
dB
CS
Channel Separation
0dBr = 100W, R
L
= 8
Ω
, f = 1kHz
85
dB
PSRR
Pow er Supply Rejection Ratio Input Ref erenced, 30kHz Bandw idth
65
dB
η
Pow er Efficiency
P
OUT
= 400W/Channel, R
L
= 8
Ω
90
%
e
NOUT
Output Noise Voltage
A Weighted, no signal, input shorted, DC
of f set nulled to zero
500
µ
V
Minimum and maximum limits are guaranteed but may not be 100% tested.
Notes:
1) V5 = +5V, VN12 = +12V referenced to V
SNEG
2) Test/Application Circuit Values:
D = MUR120T3 diodes, R
IN
= 22.1K
Ω
R
D
= 33
Ω
, R
S
= 0.025
Ω
,R
G
= 5.6
Ω
R
OCR1
= R
OCR2
= 0
Ω
, L
F
= 18uH (Amidon core T200-2)
C
F
= 0.22uF, C
D
= 0.1uF, C
IN
= 1uF, C
BY
= 0.1uF
Power Output MOSFETs, M = ST STW38NB20
BBMO=BBM1=1
3
TA104A – Rev. 3.1/06.00
Tripath Technology, Inc. - Technical Information
Pin Description
Pin
Function
Description
1
AGND
Analog Ground
2
OVERLOADB
Logic output. When low, indicates that the level of the input signal has
overloaded the amplifier.
3
V5
Positive 5 Volts
4
MUTE
Logic input. When high, both amplifiers are muted. When low (grounded), both
amplifiers are fully operational.
5, 6
IN2, IN1
Single-ended input (Channel 1 & 2)
7, 8
BBM0, BBM1
Break-before-make timing control
9, 12
GNDKELVIN1,
GNDKELVIN2
Kelvin connection to speaker ground (Channel 1 & 2)
10, 11
OCR2, OCR1
Over-current threshold adjustment (Channel 1 & 2)
13, 14
OCS1L+, OCS1L-
Over Current Sense resistor, Channel 1 low-side
15, 16
OCS1H-, OCS1H+
Over Current Sense resistor, Channel 1 high-side
17, 30
LO1COM, LO2COM
Kelvin connection to source of low-side transistor (Channel 1 & 2)
18, 29
FDBKN1;FDBKN2
Feedback (Channel 1 & 2)
19
VN12
Voltage: +12 V from V
SNEG
. Refer to Application Information section.
20, 27
LO1, LO2
Low side gate drive output (Channel 1 & 2)
21, 26
HO1COM, HO2COM Kelvin connection to source of high-side transistor (Channel 1 & 2)
22, 25
HO1, HO2
High side gate drive output (Channel 1 & 2)
23
V
SPOS
Positive supply voltage
24
V
SNEG
Negative supply voltage
28
PGND
Power Ground
31, 32
OCS2L-, OCS2L+
Over Current Sense resistor, Channel 2 low-side
33, 34
OCS2H-, OCS2H+
Over Current Sense resistor, Channel 2 high-side
35
HMUTE
Logic output. When high, indicates that the output stages of both amplifiers
are shut off and muted.
36, 37, 38
NC
Not Connected - Must Be Left Floating
38 Pin Quad Package Pin-out
(Top View)
38
37
36
35
34
33
32
31
30
29
28
1
AGND
LO2
27
2
OVERLOADB
HO2COM
26
3
V5
HO2
25
4
MUTE
V
SNEG
24
5
IN2
V
SPOS
23
6
IN1
HO1
22
7
BBM0
H01COM
21
8
BBM1
LO1
20
9
10
11
12
13
14
15
16
17
18
19
4
TA104A – Rev. 3.1/06.00
Tripath Technology, Inc. - Technical Information
Test/Application Circuit
50pF
TA0104A
18
FDBKN1
1K
16
OCS1H+
V
SPOS
R
S
.1uF
100uF
15
OCS1H-
M
D
22
HO1
C
BY
C
IN
Processing
&
Modulation
R
G
IN1
6
21
HO1COM
L
F
R
IN
M
D
20
LO1
R
D
R
L
V5
C
F
R
G
C
BY
C
D
13
OCS1L+
10K
Ω
1M
Ω
1M
Ω
17
LO1COM
R
S
0.1 uF
MUTE
4
14
OCS1L-
V
SNEG
9 GNDKELVIN1
.1uF
100uF
OCR1
11
2
OVERLOADB
R
OCR1
35
29 FDBKN2
HMUTE
50pF
OCR2
10
1K
R
OCR2
34
OCS2H+
V
SPOS
BBM0
7
R
S
100uF
BBM1
8
33
OCS2H-
M
D
25
HO2
C
BY
C
IN
Processing
&
Modulation
R
G
IN2
5
26
HO2COM
L
F
R
IN
M
D
R
D
27
LO2
R
L
V5
C
F
R
G
C
BY
C
D
32
OCS2L+
10K
Ω
1M
Ω
1M
Ω
30
LO2COM
R
S
0.1 uF
NC
36
31
OCS2L-
V
SNEG
12 GNDKELVIN2
NC
37
.1uF
100uF
23
V
SPOS
NC
38
24
V
SNEG
V5
3
19
VN12
0.1 uF
AGnd
PGnd
1
28
NC - Not Connected (Must Be Left Floating)
Note - Heavy Lines Indicate High-Current Paths
5
TA104A – Rev. 3.1/06.00
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