xapp104, mgr, Cyfra, Koparka - Ptach,Sierański, 02. Materiały wykorzystane przez dyplomantów, 06. XC95108
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//-->Application Note: FGPAsRA Quick JTAG ISP ChecklistXAPP104 (2.1) June 7, 2002SummaryIn-System Programming (ISP) circuitry is beneficial for fast prototype development. However,even the most robust circuitry needs minimal consideration to deliver the best in systemprogramming results. This application note describes a short list of considerations needed toget the best performance from your ISP designs. The list of considerations generally applies toall Xilinx ISP device families. Special considerations for Xilinx CPLDs are highlighted.FamiliesXC9500/XL/XV, XC18V00, CoolRunner™, CoolRunner-II, Spartan™-II/IIE, and Spartan-XLfamilies, as well as Virtex™ Series FPGAs and Virtex-II Series Platform FPGAs.OverviewCharge pumps, the heart of the CPLD ISP PROM circuitry, require a modest amount of care.The voltages to which the pumps must rise are directly derived from the external voltagesupplied to the VCCINT pins on the CPLD ISP PROM parts. Because these elevated voltagesmust be within their prescribed values to properly program the CPLD, it is vital that they beprovided with very clean (noise free) voltage within the right range. This suggests the first twokey rules:1. Make sure VCC is within the range specified in the device data sheet.2. Provide both 0.1NF and 0.01NF capacitors at every VCC point of the chip, attacheddirectly to the nearest ground.JTAG specifications do require pull-up resistance to be supplied internally to the TDI andTMS pins by the chips, but no particular value is required. This lets vendors supplywhatever they choose and still remain in full compliance. Because of this, very long JTAGchains or chains using parts from multiple vendors can present significant loading to theISP drive cable. In these cases, it is wise to:3. Use the latest Xilinx download cables.4. Consider including buffers on TMS or TCK signals interleaved at various points on yourJTAG circuitry to account for unknown device impedance.The Xilinx iMPACT downloading software is continuously being improved. With this in mind,it is appropriate to:5. Always be certain to use the latest version of the Xilinx iMPACT software.In some cases, XC9500/XL/XV designs appear to experience erase time or programmingtime extension as the design progresses - particularly for long chains. This is probably dueto the likely fact that parts being reprogrammed will have lots of switching signals deliveredinto them, which is different from the initial case where a blank part is being programmed.If this occurs, there is a way to lower the noise:6. Put the rest of the JTAG chain into HIGHZ when programming a troublesome part. HIGHZis a JTAG instruction that tristates the device I/O pins.© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed atAll othertrademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you mayrequire for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warrantiesor representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.XAPP104 (2.1) June 7, 2002www.xilinx.com1-800-255-77781RA Quick JTAG ISP ChecklistThis will limit the number of additional signals presented both to the system and frequentlyto a troublesome part (because parts within a given chain tend to be connected amongstthemselves). The main detail to accomplish step 6 is simply to select the HIGHZ optionfrom the iMPACT preferences selection dialog.7. If free running clocks are delivered into the ISP CPLD, it may be necessary to disconnect ordisable their entry into the CPLD while programming.This is best accomplished by using the commercially available clock generation chips thatpermit electrical disabling of the clock output. This seldom occurs, but advanced planningmakes it painless.Xilinx ISP devices support various JTAG I/O ranges. See the device data sheets for theJTAG I/O voltage level. Ensure JTAG I/O voltage compatibility between devices in the JTAGscan chain and the download cable.8. Match the download cable VCC/VREFpower supply to the JTAG I/O levels supported in theISP devices.Checklist1. Make sure VCC is within the range specified in the device data sheet.2. Provide both 0.1 and 0.01NF capacitors at every VCC point of the chip, and attacheddirectly to the nearest ground.3.Usethe latest Xilinx download cables.4. Consider including buffers on TCK and TMS interleaved at various points on your JTAGcircuitry to account for unknown device impedance.5. Always be certain to use the latest version of the Xilinx iMPACT software.6. Put the rest of the JTAG chain into HIGHZ when programming a troublesome part.7. If free running clocks are delivered into the ISP CPLD, it may be necessary to disconnect ordisable their entry into the CPLD while programming.8. Match the download cable VCC/VREFpower supply to the JTAG I/O voltage levelssupported in the ISP devices.RevisionHistoryThe following table shows the revision history for this document.Date04/14/0004/10/0206/07/02Version1.02.02.1Initial Xilinx release.Revised.Added "Virtex Series FPGAs" and "Virtex-II Series Platform FPGAs"to the Summary.Revision2www.xilinx.com1-800-255-7778XAPP104 (2.1) June 7, 2002
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